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ATmega128
Asynchronous
Operation of the
Timer/Counter
Asynchronous Status
Register – ASSR
Bit
Read/ W rite
Initial Value
7
–
R
0
6
–
R
0
5
–
R
0
4
–
R
0
3
AS0
R/ W
0
2
TCN0UB
R
0
1
OCR0UB
R
0
0
TCR0UB
R
0
ASSR
? Bit 3 – AS0: Asynchronous Timer/Counter0
W hen AS0 is written to zero, Timer/Counter0 is clocked from the I/O clock, clk I/O . W hen AS0 is
written to one, Timer/Counter is clocked from a crystal Oscillator connected to the Timer Oscilla-
tor 1 (TOSC1) pin. W hen the value of AS0 is changed, the contents of TCNT0, OCR0, and
TCCR0 might be corrupted.
? Bit 2 – TCN0UB: Timer/Counter0 Update Busy
W hen Timer/Counter0 operates asynchronously and TCNT0 is written, this bit becomes set.
W hen TCNT0 has been updated from the temporary storage register, this bit is cleared by hard-
ware. A logical zero in this bit indicates that TCNT0 is ready to be updated with a new value.
? Bit 1 – OCR0UB: Output Compare Register0 Update Busy
W hen Timer/Counter0 operates asynchronously and OCR0 is written, this bit becomes set.
W hen OCR0 has been updated from the temporary storage register, this bit is cleared by hard-
ware. A logical zero in this bit indicates that OCR0 is ready to be updated with a new value.
? Bit 0 – TCR0UB: Timer/Counter Control Register0 Update Busy
W hen Timer/Counter0 operates asynchronously and TCCR0 is written, this bit becomes set.
W hen TCCR0 has been updated from the temporary storage register, this bit is cleared by hard-
ware. A logical zero in this bit indicates that TCCR0 is ready to be updated with a new value.
If a write is performed to any of the three Timer/Counter0 Registers while its update busy flag is
set, the updated value might get corrupted and cause an unintentional interrupt to occur.
The mechanisms for reading TCNT0, OCR0, and TCCR0 are different. W hen reading TCNT0,
the actual timer value is read. W hen reading OCR0 or TCCR0, the value in the temporary stor-
age register is read.
Asynchronous
W hen Timer/Counter0 operates asynchronously, some considerations must be taken.
Operation of
Timer/Counter0
?
?
W arning: W hen switching between asynchronous and synchronous clocking of
Timer/Counter0, the Timer Registers TCNT0, OCR0, and TCCR0 might be corrupted. A
safe procedure for switching clock source is:
1. Disable the Timer/Counter0 interrupts by clearing OCIE0 and TOIE0.
2. Select clock source by setting AS0 as appropriate.
3. W rite new values to TCNT0, OCR0, and TCCR0.
4. To switch to asynchronous operation: W ait for TCN0UB, OCR0UB, and TCR0UB.
5. Clear the Timer/Counter0 interrupt flags.
6. Enable interrupts, if needed.
The Oscillator is optimized for use with a 32.768 kHz watch crystal. Applying an external
clock to the TOSC1 pin may result in incorrect Timer/Counter0 operation. The CPU main
clock frequency must be more than four times the Oscillator frequency.
106
2467X–AVR–06/11
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